SH7618 Datasheet, PDF (316/646 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7618 Series

Section 12 Ethernet Controller Direct Memory Access Controller (E-DMAC)
(a) Transmit Descriptor 0 (TD0)
TD0 indicates the transmit frame status. The CPU and E-DMAC use RD0 to report the frame
transmission status.
Initial
Bit
Bit Name value R/W Description
31
TACT
0
R/W Transmit Descriptor Active
Indicates that this descriptor is active. The CPU sets
this bit after transmit data has been transferred to the
transmit buffer. The E-DMAC resets this bit on
completion of a frame transfer or when transmission
is suspended.
0: The transmit descriptor is invalid.
Indicates that valid data has not been written to
this bit by the CPU, or this bit has been reset by a
write-back operation on termination of E-DMAC
frame transfer processing (completion or
suspension of transmission)
If this state is recognized in an E-DMAC descriptor
read, the E-DMAC terminates transmit processing
and transmit operations cannot be continued (a
restart is necessary)
1: The transmit descriptor is valid.
Indicates that valid data has been written to the
transmit buffer by the CPU and frame transfer
processing has not yet been executed, or that
frame transfer is in progress
When this state is recognized in an E-DMAC
descriptor read, the E-DMAC continues with the
transmit operation
30
TDLE
0
R/W Transmit Descriptor List End
After completion of the corresponding buffer transfer,
the E-DMAC references the first descriptor. This
specification is used to set a ring configuration for the
transmit descriptors.
0: This is not the last transmit descriptor list
1: This is the last transmit descriptor list
Rev. 6.00 Jun. 12, 2007 Page 284 of 610
REJ09B0131-0600