SH7618 Datasheet, PDF (425/646 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7618 Series

Section 15 Host Interface (HIF)
15.2 Input/Output Pins
Table 15.1 shows the HIF pin configuration.
Table 15.1 Pin Configuration
Name
HIF data pins
HIF chip select
HIF register select
HIF write
HIF read
HIF interrupt
HIF mode
HIFDMAC transfer
request
HIF boot ready
HIF pin enable
Abbreviation
HIFD15 to HIFD00
HIFCS
HIFRS
HIFWR
HIFRD
HIFINT
HIFMD
HIFDREQ
HIFRDY
HIFEBL
I/O
Description
I/O
Address, data, or command input/output to the
HIF
Input Chip select input to the HIF
Input Switching between HIF access types
0: Normal access (other than below)
1: Index register write or status register read
Input Write strobe signal. Low level is input when an
external device writes data to the HIF.
Input Read strobe signal. Low level is input when an
external device reads data from the HIF.
Output Interrupt request to an external device from
the HIF
Input
Selects whether or not this LSI is started up in
HIF boot mode. If a power-on reset is
canceled when high level is input, this LSI is
started up in HIF boot mode.
Output To an external device, DMAC transfer request
with HIFRAM as the destination
Output Indicates that the HIF reset is canceled in this
LSI and access from an external device to the
HIF can be accepted.
After 10 clock cycles (max.) of the peripheral
clock following negate of the reset input pin of
this LSI, this pin is asserted.
Input All HIF pins other than this pin are asserted by
high-level input.
Rev. 6.00 Jun. 12, 2007 Page 393 of 610
REJ09B0131-0600