SH7618 Datasheet, PDF (7/646 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7618 Series

Preface
The SH7618 Group RISC (Reduced Instruction Set Computer) microcomputers include a Renesas
Technology-original RISC CPU as its core, and the peripheral functions required to configure a
system.
Target Users: This manual was written for users who will use the SH7618 and SH7618A in the
design of application systems. Target users are expected to understand the
fundamentals of electrical circuits, logical circuits, and microcomputers.
Objective:
This manual was written to explain the hardware functions and electrical
characteristics of the SH7618 and SH7618A to the target users.
Refer to the SH-1/SH-2/SH-DSP Software Manual for a detailed description of the
instruction set.
Notes on reading this manual:
• In order to understand the overall functions of the chip
Read the manual according to the contents. This manual can be roughly categorized into parts
on the CPU, system control functions, peripheral functions and electrical characteristics.
• In order to understand the details of the CPU's functions
Read the SH-1/SH-2/SH-DSP Software Manual.
• In order to understand the details of a register when its name is known
• The addresses, bits, and initial values of the registers are summarized in section 20, List of
Registers.
Examples: Register name: The following notation is used for cases when the same or a
similar function, e.g. 16-bit timer pulse unit or serial
communication interface, is implemented on more than one
channel:
XXX_N (XXX is the register name and N is the channel
number)
Bit order:
The MSB is on the left and the LSB is on the right.
Number notation: Binary is B'xxxx, hexadecimal is H'xxxx, decimal is xxxx.
Signal notation: An overbar is added to a low-active signal: xxxx
Related Manuals:
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Rev. 6.00 Jun. 12, 2007 Page vii of xxxii