SH7618 Datasheet, PDF (133/646 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7618 Series

Section 6 Interrupt Controller (INTC)
Program
execution state
Interrupt?
Yes
User break?
Yes
No
No
NMI?
Yes
I3 to I0 ≤
level 14?
No
Yes
Save SR to stack
Save PC to stack
Copy interrupt
level to I3 to I0
Read exception
vector table
Branch to exception
handling routine
No
H-UDI
No
interrupt?
Yes
Yes
Level 15
No
interrupt?
Yes
I3 to I0 ≤
level 14?
Level 14
interrupt?
Yes
No
Yes
I3 to I0 ≤
level 13?
No
Level 1
No
interrupt?
Yes
No
Yes
I3 to I0 =
level 0?
No
Note: I3 to I0 are Interrupt mask bits in the status register (SR) of the CPU
Figure 6.3 Interrupt Sequence Flowchart
Rev. 6.00 Jun. 12, 2007 Page 101 of 610
REJ09B0131-0600