SH7618 Datasheet, PDF (17/646 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7618 Series

14.4 Operation ........................................................................................................................... 362
14.4.1 Overview............................................................................................................... 362
14.4.2 Operation in Asynchronous Mode ........................................................................ 364
14.4.3 Synchronous Mode ............................................................................................... 375
14.5 SCIF Interrupts .................................................................................................................. 383
14.6 Serial Port Register (SCSPTR) and SCIF Pins .................................................................. 384
14.7 Usage Notes ....................................................................................................................... 388
Section 15 Host Interface (HIF)...........................................................................391
15.1 Features.............................................................................................................................. 391
15.2 Input/Output Pins ............................................................................................................... 393
15.3 Parallel Access ................................................................................................................... 394
15.3.1 Operation .............................................................................................................. 394
15.3.2 Connection Method............................................................................................... 394
15.4 Register Descriptions ......................................................................................................... 395
15.4.1 HIF Index Register (HIFIDX) .............................................................................. 395
15.4.2 HIF General Status Register (HIFGSR)................................................................ 398
15.4.3 HIF Status/Control Register (HIFSCR) ................................................................ 398
15.4.4 HIF Memory Control Register (HIFMCR) ........................................................... 401
15.4.5 HIF Internal Interrupt Control Register (HIFIICR) .............................................. 403
15.4.6 HIF External Interrupt Control Register (HIFEICR) ............................................ 403
15.4.7 HIF Address Register (HIFADR) ......................................................................... 404
15.4.8 HIF Data Register (HIFDATA) ............................................................................ 405
15.4.9 HIF Boot Control Register (HIFBCR).................................................................. 405
15.4.10 HIFDREQ Trigger Register (HIFDTR) ................................................................ 406
15.4.11 HIF Bank Interrupt Control Register (HIFBICR) ................................................. 407
15.5 Memory Map ..................................................................................................................... 409
15.6 Interface (Basic)................................................................................................................. 410
15.7 Interface (Details) .............................................................................................................. 411
15.7.1 HIFIDX Write/HIFGSR Read .............................................................................. 411
15.7.2 Reading/Writing of HIF Registers other than HIFIDX and HIFGSR................... 411
15.7.3 Consecutive Data Writing to HIFRAM by External Device................................. 412
15.7.4 Consecutive Data Reading from HIFRAM to External Device ............................ 412
15.8 External DMAC Interface.................................................................................................. 413
15.9 Interface When External Device Power is Cut Off ............................................................ 419
Section 16 Pin Function Controller (PFC)...........................................................423
16.1 Register Descriptions ......................................................................................................... 432
16.1.1 Port A IO Register H (PAIORH) .......................................................................... 433
16.1.2 Port A Control Register H1 and H2 (PACRH1 and PACRH2) ............................ 433
Rev. 6.00 Jun. 12, 2007 Page xvii of xxxii