SH7618 Datasheet, PDF (171/646 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7618 Series

Section 7 Bus State Controller (BSC)
Initial
Bit
Bit Name Value R/W Description
2
RRC2
0
R/W Refresh Count
1
RRC1
0
R/W Specify the number of consecutive refresh cycles, when
0
RRC0
0
R/W ^{the refresh request occurs after the coincidence of the}
values of the refresh timer counter (RTCNT) and the
refresh time constant register (RTCOR). Using
consecutive refresh cycles can prolong cycles between
refreshing.
000: Once
001: Twice
010: 4 times
011: 6 times
100: 8 times
101: Reserved (setting prohibited)
110: Reserved (setting prohibited)
111: Reserved (setting prohibited)
7.4.6 Refresh Timer Counter (RTCNT)
RTCNT is an 8-bit counter that increments using the clock selected by bits CKS2 to CKS0 in
RTCSR. When RTCNT matches RTCOR, RTCNT is cleared to 0. The value in RTCNT returns
to 0 after counting up to 255. When RTCNT is written to, the upper 16 bits of the write data must
be H'A55A to cancel write protection.
Bit
31 to 8
Initial
Bit Name Value R/W

All 0 R
7 to 0 
All 0 R/W
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
8-bit Counter
Rev. 6.00 Jun. 12, 2007 Page 139 of 610
REJ09B0131-0600