SH7618 Datasheet, PDF (614/646 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7618 Series

Section 21 Electrical Characteristics
21.4.9 HIF Timing
Table 21.12 HIF Timing
Conditions: V_CCQ = 3.0 V to 3.6 V, V_CC = 1.4 V to 1.6 V,
T_a = –20°C to +75°C (regular specifications),
T_a = –40°C to +85°C (wide-range specifications)
Item
Symbol Min.
Max.
Unit Reference Figures
Read bus cycle time
t_HIFCYCR
4

t_pcyc
Figure 21.40
Write bus cycle time
t_HIFCYCW
4

t_pcyc
Address setup time (HIFSCR.DMD = 0) t_HIFAS
10

ns
Address setup time (HIFSCR.DMD = 1) t_HIFAS
0

ns
Address hold time (HIFSCR.DMD = 0) t_HIFAH
10

ns
Address hold time (HIFSCR.DMD = 1) t_HIFAH
0

ns
Read low width (read)
t_HIFWRL
2.5

t_pcyc
Write low width (write)
t_HIFWWL
2.5

t_pcyc
Read/write high width
t_HIFWRWH
2.0

t_pcyc
Read data delay time
t_HIFRDD

2 × t_pcyc + 16 ns
Read data hold time
t_HIFRDH
0

ns
Write data setup time
t_HIFWDS
t_pcyc + 10

ns
Write data hold time
t_HIFWDH
10

ns
HIFINT output delay time
t_HIFITD

20
ns
Figure 21.41
HIFRDY output delay time
t_HIFRYD

10
t_pcyc
Figure 21.42
HIFDREQ output delay time
t_HIFDQD

20
ns
Figure 21.41
HIF pin enable delay time
t_HIFEBD

20
ns
Figure 21.42
HIF pin disable delay time
t_HIFDBD

20
ns
Notes:
1.
t
pcyc
indicates
the
period
of
the
peripheral
module
clock
(Pφ).
2. t is given from the start of the time over which both the HIFCS and HIFRD (or
HIFAS
HIFWR) signals are low levels.
3. t_HIFAH is given from the end of the time over which both the HIFCS and HIFRD (or
HIFWR) signals are low levels.
4. t is given as the time over which both the HIFCS and HIFRD signals are low levels.
HIFWRL
5. t is given as the time over which both the HIFCS and HIFWR signals are low levels.
HIFWWL
6. When reading the register specified by bits REG5 to REG0 after writing to the HIF index
register
(HIFIDX),
t
HIFWRWH
(min.)
=
2
×
t
pcyc
+
5
ns.
Rev. 6.00 Jun. 12, 2007 Page 582 of 610
REJ09B0131-0600