SH7618 Datasheet, PDF (636/646 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7618 Series

Item
Page Revision (See Manual for Details)
Figure 21.29 Synchronous
572
DRAM Burst Write Bus Cycle
(Single Write × 4)
(Bank Active Mode: PRE + ACT +
WRITE Commands, Different Row
Addresses,
WTRCD = 0 Cycle, TRWL = 0
Cycle)
Amended
CKIO
A25 to A0
Tp
tAD1
Tpw
Tr
Tc1
Tc2
Tc3
Tc4
Row address
tAD1
tAD1
tAD1
tAD1
tAD1
Column
address
Column
address
Column
address
Column
address
Figure 21.30 Synchronous
DRAM Auto-Refreshing Timing
(WTRP = 1 Cycle, WTRC = 3
Cycles)
573 Amended
CKIO
Tp
Tap
Trr
Trc
Trc
Trc
tAD1
tAD1
A25 to A0
Figure 21.31 Synchronous
DRAM Self-Refreshing Timing
(WTRP = 1 Cycle)
574
Amended
CKIO
A25 to A0
Tp
tAD1
Tap
Trr
Trc
tAD1
Trc
Trc
Trc
Trc
Figure 21.32 Synchronous
DRAM Mode Register Write
Timing (WTRP = 1 Cycle)
575
Amended
CKIO
Tp
Tap
Trr
Trc
PALL
tAD1
REF
A25 to A0
Trc
Trr
Trc
REF
Trc Tmw
Tde
MRS
tAD1
tAD1
Rev. 6.00 Jun. 12, 2007 Page 604 of 610
REJ09B0131-0600