SH7618 Datasheet, PDF (135/646 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7618 Series

Section 6 Interrupt Controller (INTC)
Table 6.3 Interrupt Response Time
Number of Cycles
Item
NMI, H-UDI
IRQ, Peripheral
Modules
Remarks
Interrupt priority decision
and comparison with mask
bits in SR
1 × Icyc + 2 × Pcyc 1 × Icyc + 3 × Pcyc
Wait for completion of
sequence currently being
executed by CPU
X (≥ 0)
X (≥ 0)
The longest sequence
is for interrupt or
address-error
exception handling (X =
7 × Icyc + m1 + m2
+ m3 + m4). If an
interrupt-masking
instruction follows,
however, the time may
be even longer.
Time from start of interrupt
exception handling until
fetch of first instruction of
exception handling routine
starts
8 × Icyc + m1 + m2 8 × Icyc + m1 + m2
+ m3
+ m3
Performs the saving
PC and SR, and vector
address fetch.
Interrupt
response
time
Total: 9 × Icyc + 2 × Pcyc 9 × Icyc + 3 × Pcyc
+ m1 + m2 + m3 + m1 + m2 + m3
+X
+X
Minimum*: 12 × Icyc +
2 × Pcyc
12 × Icyc +
3 × Pcyc
SR, PC, and vector
table are all in on-chip
RAM, or cache hit
occurs (in write back
mode).
Maximum:
16 × Icyc +
2 × Pcyc + 2 ×
(m1 + m2 + m3) +
m4
16 × Icyc +
3 × Pcyc + 2 ×
(m1 + m2 + m3) +
m4
Notes: *
In the case that m1 = m2 = m3 = m4 = 1 × Icyc.
m1 to m4 are the number of cycles needed for the following memory accesses.
m1: SR save (longword write)
m2: PC save (longword write)
m3: Vector address read (longword read)
m4: Fetch first instruction of interrupt service routine
Rev. 6.00 Jun. 12, 2007 Page 103 of 610
REJ09B0131-0600