SH7618 Datasheet, PDF (413/646 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7618 Series

Section 14 Serial Communication Interface with FIFO (SCIF)
In receiving, the SCIF operates as follows:
1. The SCIF synchronizes with serial clock input or output and initializes internally.
2. Receive data is shifted into SCRSR in order from the LSB to the MSB. After receiving the
data, the SCIF checks the receive data can be loaded from SCRSR into SCFRDR or not. If this
check is passed, the SCIF stores the received data in SCFRDR. If the check is not passed
(overrun error is detected), further reception is prevented.
3. After setting RDF to 1, if the receive-data-full interrupt enable bit (RIE) is set to 1 in SCSCR,
the SCIF requests a receive-data-full interrupt (RXI). If the ORER bit is set to 1 and the RIE
bit or REIE bit in SCSCR is also set to 1, the SCIF requests a break interrupt (BRI).
Figure 14.17 shows an example of SCIF receive operation.
Synchronization
clock
Serial data
LSB
Bit 7 Bit 0
MSB
Bit 7
Bit 0
Bit 1
Bit 6 Bit 7
RDF
ORER
RXI Data read from _RXI
interrupt SCFRDR and _interrupt
request RDF flag cleared _request
to 0 by RXI
interrupt handler
One frame
BRI interrupt request
by overrun error
Figure 14.17 Example of SCIF Receive Operation
Rev. 6.00 Jun. 12, 2007 Page 381 of 610
REJ09B0131-0600