SH7618 Datasheet, PDF (100/646 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7618 Series

Section 5 Exception Handling
Exception Handling Source
Vector Number Vector Table Address Offset
Trap instruction (user vector)
32
H'00000080 to H'00000083
:
:
63
H'000000FC to H'000000FF
Interrupt
IRQ0
64
H'00000100 to H'00000103
IRQ1
65
H'00000104 to H'00000107
IRQ2
66
H'00000108 to H'0000010B
IRQ3
67
H'0000010C to H'0000010F
(Reserved by system) 68
H'00000110 to H'00000113
:
:
79
H'0000013C to H'0000013F
IRQ4
80
H'00000140 to H'00000143
IRQ5
81
H'00000144 to H'00000147
IRQ6
82
H'00000148 to H'0000014B
IRQ7
83
H'0000014C to H'0000014F
On-chip peripheral module*
84
H'00000120 to H'00000124
:
:
255
H'000003FC to H'000003FF
Note: * For details on the vector numbers and vector table address offsets of on-chip peripheral
module interrupts, see table 6.2, Interrupt Exception Handling Vectors and Priorities in
section 6, Interrupt Controller (INTC).
Table 5.4 Calculating Exception Handling Vector Table Addresses
Exception Source
Vector Table Address Calculation
Resets
Vector table address = H'A0000000 + (vector table address offset)
= H'A0000000 + (vector number) × 4
Address errors, interrupts,
instructions
Vector table address = VBR + (vector table address offset)
= VBR + (vector number) × 4
Notes: 1. VBR: Vector base register
2. Vector table address offset: See table 5.3.
3. Vector number: See table 5.3.
Rev. 6.00 Jun. 12, 2007 Page 68 of 610
REJ09B0131-0600