SH7618 Datasheet, PDF (310/646 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7618 Series

Section 12 Ethernet Controller Direct Memory Access Controller (E-DMAC)
12.2.12 Receiving method Control Register (RMCR)
RMCR is a 32-bit readable/writable register that specifies the control method for the RR bit in
EDRRR when a frame is received. This register must be set during the receiving-halt state.
Initial
Bit
Bit Name value R/W Description
31 to 1 
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
0
RNC
0
R/W Receive Enable Control
0: When reception of one frame is completed, the E-
DMAC writes the receive status into the descriptor
and clears the RR bit in EDRRR
1: When reception of one frame is completed, the E-
DMAC writes the receive status into the descriptor,
reads the next descriptor, and prepares to receive
the next frame
Rev. 6.00 Jun. 12, 2007 Page 278 of 610
REJ09B0131-0600