SH7618 Datasheet, PDF (294/646 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7618 Series

Section 12 Ethernet Controller Direct Memory Access Controller (E-DMAC)
Initial
Bit
Bit Name value R/W Description
0
SWR
0
R/W Software Reset
Writing 1 in this bit initializes registers of the E-DMAC
other than TDLAR, RDLAR, and RMFCR and registers
of the EtherC. While a software reset is issued (64
cycles of the internal bus clock Bφ), accesses to the all
Ethernet-related registers are prohibited.
Software reset period (example):
When Bφ = 50 MHz: 1.28 µS
When Bφ = 33 MHz: 1.94 µS
This bit is always read as 0.
0: Writing 0 is ignored (E-DMAC operation is not
affected)
1: Writing 1 resets the EtherC and E-DMAC and then
automatically cleared
12.2.2 E-DMAC Transmit Request Register (EDTRR)
The EDTRR is a 32-bit readable/writable register that issues transmit directives to the E-DMAC.
When transmission of one frame is completed, the next descriptor is read. If the transmit
descriptor active bit in this descriptor has the "active" setting, transmission is continued. If the
transmit descriptor active bit has the "inactive" setting, the TR bit is cleared and operation of the
transmit DMAC is halted.
Bit
Bit Name
31 to 1 
0
TR
Initial
value
All 0
0
R/W Description
R
Reserved
These bits are always read as 0. The write value should
always be 0.
R/W Transmit Request
0: Transmission-halted state. Writing 0 does not stop
transmission. Termination of transmission is
controlled by the active bit in the transmit descriptor
1: Start of transmission. The relevant descriptor is read
and a frame is sent with the transmit active bit set to
1
Rev. 6.00 Jun. 12, 2007 Page 262 of 610
REJ09B0131-0600