SH7618 Datasheet, PDF (631/646 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7618 Series

Main Revisions and Additions in this Edition
Item
1. Auto-refreshing
14.3.7 Serial Status Register
(SCFSR)
Page Revision (See Manual for Details)
175 Amended
:
set so as to satisfy the SDRAM refreshing cycle time
(tRC). A Tpw cycle is inserted between the Tp cycle
and Trr cycle when the setting of bits WTRP1 and
WTRP0 in CSnWCR is longer than or equal to one
cycle.
341 Amended
Mode Description
5
Transmit FIFO Data Empty
Indicates that data has been transferred from the transmit FIFO
data register (SCFTDR) to the transmit shift register (SCTSR), the
quantity of data in SCFTDR has become less than the transmission
trigger number specified by the TTRG1 and TTRG0 bits in the FIFO
control register (SCFCR), and writing of transmit data to SCFTDR is
enabled.
0: The quantity of transmit data written to SCFTDR is greater than
the specified transmission trigger number
[Clearing conditions]
• TDFE is cleared to 0 when data exceeding the specified
transmission trigger number is written to SCFTDR after 1 is
read from TDFE and then 0 is written
• TDFE is cleared to 0 when DMAC write data exceeding the
specified transmission trigger number to SCFTDR
1: The quantity of transmit data in SCFTDR is equal to or less than
the specified transmission trigger number*
[Setting conditions]
• TDFE is set to 1 by a power-on reset
• TDFE is set to 1 when the quantity of transmit data in
SCFTDR has become equal to or less than the specified
transmission trigger number as a result of transmission
Note: *
Since SCFTDR is a 16-byte FIFO register, the
maximum quantity of data that can be written when TDFE is 1 is "16
minus the specified transmission trigger number". If an attempt is
made to write additional data, the data is ignored. The quantity of
data in SCFTDR is indicated by the upper 8 bits of SCFDR.
Rev. 6.00 Jun. 12, 2007 Page 599 of 610
REJ09B0131-0600