SH7618 Datasheet, PDF (148/646 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7618 Series

Section 7 Bus State Controller (BSC)
Initial
Bit
Bit Name Value R/W Description
27

0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
26
IWRWD1 1
R/W Idle Cycles for Another Space Read-Write
25
IWRWD0 1
R/W Specify the number of idle cycles to be inserted after the
access to a memory that is connected to the area. The
read and write cycles which are performed consecutively
and are accessed to different areas are the target cycle.
000: No idle cycle inserted
001: 1 idle cycles inserted
010: 2 idle cycles inserted
011: 4 idle cycles inserted
24

0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
23
IWRWS1 1
R/W Idle Cycles for Read-Write in Same Space
22
IWRWS0 1
R/W Specify the number of idle cycles to be inserted after the
access to a memory that is connected to the area. The
read and write cycles which are performed consecutively
and are accessed to the same area are the target cycle.
000: No idle cycle inserted
001: 1 idle cycles inserted
010: 2 idle cycles inserted
011: 4 idle cycles inserted
21

0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
Rev. 6.00 Jun. 12, 2007 Page 116 of 610
REJ09B0131-0600