SH7618 Datasheet, PDF (251/646 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7618 Series

Section 10 Power-Down Modes
10.3.2 Standby Control Register 2 (STBCR2)
STBCR2 is an 8-bit readable/writable register that controls the operation of modules in power-
down mode.
Initial
Bit
Bit Name Value R/W
7
MSTP10 0
R/W
6
MSTP9
0
R/W
5 to 3 
All 0
R
2
MSTP5
0
R/W
1
MSTP4
0
R/W
0

0
R
Description
Module Stop Bit 10
When this bit is set to 1, the supply of the clock to
the H-UDI is halted.
0: H-UDI operates
1: Clock supply to H-UDI halted
Module Stop Bit 9
When this bit is set to 1, the supply of the clock to
the UBC is halted.
0: UBC operates
1: Clock supply to UBC halted
Reserved
These bits are always read as 0. The write value
should always be 0.
Module Stop Bit 5
When this bit is set to 1, the supply of the clock to
the cache memory is halted.
0: Cache memory operates
1: Clock supply to cache memory halted
Module Stop Bit 4
When this bit is set to 1, the supply of the clock to
the U memory is halted.
0: U memory operates
1: Clock supply to the U memory halted
Reserved
This bit is always read as 0. The write value should
always be 0.
Rev. 6.00 Jun. 12, 2007 Page 219 of 610
REJ09B0131-0600