SH7618 Datasheet, PDF (35/646 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7618 Series

Section 1 Overview
Bus state controller (BSC):
• Address space is divided into five areas: three areas 0, 3, and 4; each a maximum of 64
Mbytes, and two areas 5B and 6B; each a maximum of 32 Mbytes (address map 1 mode).
• Address space is divided into five areas, 0, 3, 4, 5, and 6; each a maximum of 64 Mbytes
(address map 2 mode).
• 16-bit external bus
• The following features are settable for each area.
 Bus size (8 or 16 bits)
 Number of access wait cycles
 Setting of idle wait cycles
 Specifying the memory to be connected to each area enables direct connection to SRAM,
SDRAM, and PCMCIA.
 Outputs chip select signals (CS0, CS3, CS4, CS5B, and CS6B) for corresponding area
• SDRAM refresh function
 Supports auto-refresh and self-refresh modes
• SDRAM burst access function
• PCMCIA access function
 Conforms to the JEIDA Ver. 4.2 standard, two slots
• Selection of big or little endian mode (The mode of all the areas is switched collectively by a
mode pin.)
Interrupt controller (INTC):
• Supports nine external interrupt pins (NMI, IRQ7 to IRQ0)
• On-chip peripheral interrupt: Priority level is independently selected for each module
• Vector address: Specified vector address for each interrupt source
User debugging interface (H-UDI):
• Supports the JTAG interface emulator
• JTAG standard pins arranged
Clock pulse generator (CPG):
• Clock mode: Clock source selectable between an external supply and crystal resonator
• Three types of clocks generated:
 CPU clock: 100 MHz (max.)
 Bus clock: 50 MHz (max.)
Rev. 6.00 Jun. 12, 2007 Page 3 of 610
REJ09B0131-0600