SH7618 Datasheet, PDF (26/646 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7618 Series

Figure 21.18 Synchronous DRAM Burst Read Bus Cycle (Single Read × 4)
(Auto-Precharge, CAS Latency = 2, WTRCD = 0 Cycle, WTRP = 1 Cycle)....... 561
Figure 21.19 Synchronous DRAM Burst Read Bus Cycle (Single Read × 4)
(Auto-Precharge, CAS Latency = 2, WTRCD = 1 Cycle, WTRP = 0 Cycle)....... 562
Figure 21.20 Synchronous DRAM Single Write Bus Cycle
(Auto-Precharge, TRWL = 1 Cycle)..................................................................... 563
Figure 21.21 Synchronous DRAM Single Write Bus Cycle
(Auto-Precharge, WTRCD = 2 Cycles, TRWL = 1 Cycle)................................... 564
Figure 21.22 Synchronous DRAM Burst Write Bus Cycle (Single Write × 4)
(Auto-Precharge, WTRCD = 0 Cycle, TRWL = 1 Cycle) .................................... 565
Figure 21.23 Synchronous DRAM Burst Write Bus Cycle (Single Write × 4)
(Auto-Precharge, WTRCD = 1 Cycle, TRWL = 1 Cycle) .................................... 566
Figure 21.24 Synchronous DRAM Burst Read Bus Cycle (Single Read × 4)
(Bank Active Mode: ACT + READ Commands, CAS Latency = 2,
WTRCD = 0 Cycle) .............................................................................................. 567
Figure 21.25 Synchronous DRAM Burst Read Bus Cycle (Single Read × 4)
(Bank Active Mode: READ Command, Same Row Address, CAS Latency = 2,
WTRCD = 0 Cycle) .............................................................................................. 568
Figure 21.26 Synchronous DRAM Burst Read Bus Cycle (Single Read × 4)
(Bank Active Mode: PRE + ACT + READ Commands, Different Row Addresses,
CAS Latency = 2, WTRCD = 0 Cycle)................................................................. 569
Figure 21.27 Synchronous DRAM Burst Write Bus Cycle (Single Write × 4)
(Bank Active Mode: ACT + WRITE Commands, WTRCD = 0 Cycle,
TRWL = 0 Cycle) ................................................................................................. 570
Figure 21.28 Synchronous DRAM Burst Write Bus Cycle (Single Write × 4)
(Bank Active Mode: WRITE Command, Same Row Address, WTRCD = 0 Cycle,
TRWL = 0 Cycle) ................................................................................................. 571
Figure 21.29 Synchronous DRAM Burst Write Bus Cycle (Single Write × 4)
(Bank Active Mode: PRE + ACT + WRITE Commands, Different Row Addresses,
WTRCD = 0 Cycle, TRWL = 0 Cycle)................................................................. 572
Figure 21.30 Synchronous DRAM Auto-Refreshing Timing
(WTRP = 1 Cycle, WTRC = 3 Cycles)................................................................. 573
Figure 21.31 Synchronous DRAM Self-Refreshing Timing (WTRP = 1 Cycle) ....................... 574
Figure 21.32 Synchronous DRAM Mode Register Write Timing (WTRP = 1 Cycle)............... 575
Figure 21.33 PCMCIA Memory Card Interface Bus Timing ..................................................... 576
Figure 21.34 PCMCIA Memory Card Interface Bus Timing (TED = 2.5 Cycles,
TEH = 1.5 Cycles, One Software Wait Cycle, One External Wait Cycle) ........... 577
Figure 21.35 PCMCIA I/O Card Interface Bus Timing.............................................................. 578
Figure 21.36 PCMCIA I/O Card Interface Bus Timing (TED = 2.5 Cycles, TEH = 1.5 Cycles,
One Software Wait Cycle, One External Wait Cycle) .......................................... 579
Rev. 6.00 Jun. 12, 2007 Page xxvi of xxxii