SH7618 Datasheet, PDF (93/646 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7618 Series

Section 3 Cache
3.4.3 Usage Examples
Invalidating Specific Entries: Specific cache entries can be invalidated by writing 0 to the entry's
V bit in the memory-mapped cache access. When the A bit is 1, the tag address specified by the
write data is compared to the tag address within the cache selected by the entry address, and the V
bit and U bit specified by the write data are written when a match is found. If no match is found,
there is no operation. When the V bit of an entry in the address array is set to 0, the entry is written
back if the entry's U bit is 1. In the example shown below, R0 specifies the write data and R1
specifies the address.
; R0=H'01100010; VPN=B'0000 0001 0001 0000 0000 00, U=0, V=0
; R1=H'F0000088; address array access, entry=B'001000
(entry=B'00001000 for the SH7618A), A=1
;
MOV.L R0,@R1
Reading Data of Specific Entry: The data section of a specific entry can be read from by the
memory-mapped cache access. The longword indicated in the data field of the data array in
figure 3.4 is read into the register. In the example shown below, R0 specifies the address and R1
shows what is read.
; R0=H'F100004C; data array access, entry=B'000100
(entry=B'00000100 for the SH7618A)
; Way = 0, longword address = 3
;
MOV.L @R0,R1 ; Longword 3 is read.
Rev. 6.00 Jun. 12, 2007 Page 61 of 610
REJ09B0131-0600