SH7618 Datasheet, PDF (112/646 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7618 Series

Section 5 Exception Handling
Compiler
This instruction is not allocated in the delay slot in the compiler V.4 or later versions.
Real-time OS for µITRON specifications
1. HI7000/4, HI-SH7
This instruction does not exist in the delay slot within the OS.
2. HI7000
This instruction is in part allocated to the delay slot within the OS, which may cause the slot
illegal instruction exception handling in this LSI.
3. Others
The slot illegal instruction exception handling may be generated in this LSI in case where the
instruction is described in assembler or when the middleware of the object is introduced.
Note that a check-up program (checker) to pick up this instruction is available on our website.
Download and utilize this checker as needed.
Rev. 6.00 Jun. 12, 2007 Page 80 of 610
REJ09B0131-0600