SH7618 Datasheet, PDF (523/646 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7618 Series

Section 18 User Break Controller (UBC)
Break Condition Specified for L Bus Data Access Cycle:
• Register specifications
BARA = H'00123456, BAMRA = H'00000000, BBRA = H'0064, BARB = H'000ABCDE,
BAMRB = H'000000FF, BBRB = H'006A, BDRB = H'0000A512, BDMRB = H'00000000,
BRCR = H'00000080
Specified conditions: Channel A/channel B independent mode
 Channel A
Address: H'00123456, Address mask: H'00000000, ASID = H'80
Bus cycle: L bus/data access/read (operand size is not included in the condition)
 Channel B
Address: H'000ABCDE, Address mask: H'000000FF
Data: H'0000A512, Data mask: H'00000000
Bus cycle: L bus/data access/write/word
On channel A, a user break occurs with longword read from address H'00123454, word read
from address H'00123456, or byte read from address H'00123456. On channel B, a user break
occurs when word H'A512 is written in addresses H'000ABC00 to H'000ABCFE.
Break Condition Specified for I Bus Data Access Cycle:
• Register specifications:
BARA = H'00314156, BAMRA = H'00000000, BBRA = H'0094, BARB = H'00055555,
BAMRB = H'00000000, BBRB = H'00A9, BDRB = H'00007878, BDMRB = H'00000F0F,
BRCR = H'00000080
Specified conditions: Channel A/channel B independent mode
 Channel A
Address: H'00314156, Address mask: H'00000000, ASID = H'80
Bus cycle: I bus/instruction fetch/read (operand size is not included in the condition)
 Channel B
Address: H'00055555, Address mask: H'00000000, ASID = H'70
Data: H'00000078, Data mask: H'0000000F
Bus cycle: I bus/data access/write/byte
On channel A, a user break occurs when instruction fetch is performed for address H'00314156
in the memory space.
On channel B, a user break occurs when the I bus writes byte data H'7* in address
H'00055555.
Rev. 6.00 Jun. 12, 2007 Page 491 of 610
REJ09B0131-0600