SH7618 Datasheet, PDF (196/646 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7618 Series

Section 7 Bus State Controller (BSC)
Single Read: A read access ends in one cycle when data exists in non-cacheable area and the data
bus width is larger than or equal to access size. Since the burst length is set to 1 in synchronous
DRAM burst read/single write mode, only the required data is output. Consequently, no
unnecessary bus cycles are generated even when a cache-through area is accessed.
Figure 7.14 shows the single read basic timing.
CKIO
A25 to A0
A11*
CSn
RAS
CAS
RD/WR
DQMxx
D15 to D0
BS
Tr
Tc1
Td1
Tde
Tap
Note: * Address pin to be connected to pin A10 of SDRAM.
Figure 7.14 Basic Timing for Single Read (Auto Precharge)
Rev. 6.00 Jun. 12, 2007 Page 164 of 610
REJ09B0131-0600