SH7618 Datasheet, PDF (23/646 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7618 Series

Figure 11.4 (1) MII Frame Transmit Timing (Normal Transmission)........................................ 250
Figure 11.4 (2) MII Frame Transmit Timing (Collision)............................................................ 250
Figure 11.4 (3) MII Frame Transmit Timing (Transmit Error)................................................... 251
Figure 11.4 (4) MII Frame Receive Timing (Normal Reception)............................................... 251
Figure 11.4 (5) MII Frame Receive Timing (Reception Error (1))............................................. 251
Figure 11.4 (6) MII Fame Receive Timing (Reception Error (2)) .............................................. 251
Figure 11.5 MII Management Frame Format ............................................................................. 252
Figure 11.6 (1) 1-Bit Data Write Flowchart ............................................................................... 253
Figure 11.6 (2) Bus Release Flowchart (TA in Read in Figure 11.5) ......................................... 254
Figure 11.6 (3) 1-Bit Data Read Flowchart ................................................................................ 254
Figure 11.6 (4) Independent Bus Release Flowchart (IDLE in Write in Figure 11.5)................ 255
Figure 11.7 Changing IPG and Transmission Efficiency ........................................................... 256
Figure 11.8 Example of Connection to DP83846AVHG............................................................ 257
Section 12 Ethernet Controller Direct Memory Access Controller (E-DMAC)
Figure 12.1 Configuration of E-DMAC, and Descriptors and Buffers....................................... 259
Figure 12.2 Relationship between Transmit Descriptor and Transmit Buffer ............................ 283
Figure 12.3 Relationship between Receive Descriptor and Receive Buffer ............................... 287
Figure 12.4 Sample Transmission Flowchart ............................................................................. 292
Figure 12.5 Sample Reception Flowchart................................................................................... 294
Figure 12.6 E-DMAC Operation after Transmit Error ............................................................... 295
Figure 12.7 E-DMAC Operation after Receive Error................................................................. 296
Figure 12.8 Timing of the Case where Setting of the Interrupt Source Bit in EESR
by the E-DMAC Fails............................................................................................. 297
Figure 12.9 Countermeasure by Monitoring the Transmit Descriptor in Processing
of Interrupts Other than the Frame Transmit Complete (TC) Interrupt.................. 303
Figure 12.10 Method of Adding Timeout Processing................................................................. 305
Figure 12.11 Operation when E-DMAC Stops and the Transmit FIFO ..................................... 307
Figure 12.12 Processing Transmission without Handling of the TC Interrupt ........................... 310
Figure 12.13 Countermeasure for the Case with TC Interrupt-Driven Software:
Addition of Timeout Processing within the Limit Imposed by the
Maximum Specified Time..................................................................................... 313
Section 13 Compare Match Timer (CMT)
Figure 13.1 Block Diagram of Compare Match Timer............................................................... 315
Figure 13.2 Counter Operation ................................................................................................... 319
Figure 13.3 Count Timing .......................................................................................................... 319
Figure 13.4 Timing of CMF Setting ........................................................................................... 320
Figure 13.5 Conflict between Write and Compare-Match Processes of CMCNT ...................... 321
Figure 13.6 Conflict between Word-Write and Count-Up Processes of CMCNT...................... 322
Figure 13.7 Conflict between Byte-Write and Count-Up Processes of CMCNT ....................... 323
Rev. 6.00 Jun. 12, 2007 Page xxiii of xxxii