SH7618 Datasheet, PDF (255/646 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7618 Series

Section 10 Power-Down Modes
10.5 Software Standby Mode
10.5.1 Transition to Software Standby Mode
This LSI switches from a program execution state to software standby mode by executing the
SLEEP instruction when the STBY bit in STBCR is 1. In software standby mode, not only the
CPU but also the clock and on-chip peripheral modules halt. The clock output from the CKIO pin
also halts.
The contents of the CPU and cache registers remain unchanged. Some registers of on-chip
peripheral modules are, however, initialized. Table 10.3 lists the states of on-chip peripheral
modules registers in software standby mode.
Table 10.3 Register States in Software Standby Mode
Module
Interrupt controller (INTC)
Clock pulse generator (CPG)
User break controller (UBC)
Bus state controller (BSC)
Ethernet controller (EtherC)
Direct memory access controller for
Ethernet controller (E-DMAC)
I/O port
User debugging interface (H-UDI)
Serial communication interface with FIFO
(SCIF0 to SCIF2)
Compare match timer (CMT0 and CMT1)
Host interface (HIF)
Registers Initialized









All registers

Registers Retaining
Data
All registers
All registers
All registers
All registers
All registers
All registers
All registers
All registers
All registers

All registers
Rev. 6.00 Jun. 12, 2007 Page 223 of 610
REJ09B0131-0600