SH7618 Datasheet, PDF (508/646 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7618 Series

Section 18 User Break Controller (UBC)
18.2.5 Break Address Mask Register B (BAMRB)
BAMRB is a 32-bit readable/writable register. BAMRB specifies bits masked in the break address
specified by BARB.
Initial
Bit
Bit Name Value R/W
31 to 0 BAMB31 All 0 R/W
to
BAMB 0
Description
Break Address Mask B
Specifies bits masked in the break address of channel B
specified by BARB (BAB31 to BAB0).
0: Break address BABn of channel B is included in the
break condition
1: Break address BABn of channel B is masked and is
not included in the break condition
Note: n = 31 to 0
18.2.6 Break Data Register B (BDRB)
BDRB is a 32-bit readable/writable register. BDBR selects data used for a break condition in
channel B.
Initial
Bit
Bit Name Value R/W Description
31 to 0 BDB31 to
BDB 0
All 0 R/W Break Data Bit B
Stores data which specifies a break condition in
channel B.
BDRB specifies the break data on LDB or IDB.
Notes: 1. Specify an operand size when including the value of the data bus in the break condition.
2. When the byte size is selected as a break condition, the same byte data must be set in
bits 15 to 8 and 7 to 0 in BDRB as the break data.
Rev. 6.00 Jun. 12, 2007 Page 476 of 610
REJ09B0131-0600