SH7618 Datasheet, PDF (86/646 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7618 Series

Section 3 Cache
3.3 Operation
3.3.1 Searching Cache
If the cache is enabled (the CE bit in CCR1 is set to 1), whenever an instruction or data in
H'00000000 to H'7FFFFFFF, H'8000000 to H'9FFFFFFF, and H'C0000000 to H'DFFFFFFF is
accessed, the cache will be searched to see if the desired instruction or data is in the cache. Figure
3.2 illustrates the method by which the cache is searched.
Entries are selected using bits 9 to 4 (bits 11 to 4 for the SH7618A) of the memory access address
and the tag address of that entry is read. The address comparison is performed on all four ways.
When the comparison shows a match and the selected entry is valid (V = 1), a cache hit occurs.
When the comparison does not show a match or the selected entry is not valid (V = 0), a cache
miss occurs. Figure 3.2 shows a hit on way 1.
Rev. 6.00 Jun. 12, 2007 Page 54 of 610
REJ09B0131-0600