SH7618 Datasheet, PDF (33/646 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7618 Series

Section 1 Overview
Section 1 Overview
This LSI is a CMOS single-chip microcontroller that integrates a high-speed CPU core using an
original Renesas Technology RISC (Reduced Instruction Set Computer) architecture with
supporting functions required for an Ethernet system.
The CPU of this LSI has a RISC (Reduced Instruction Set Computer) type instruction set. The
CPU basically operates at a rate of one instruction per cycle, offering a great improvement in
instruction execution speed. In addition, the 32-bit internal architecture provides improved data
processing power. With this CPU, it has become possible to assemble low-cost, high-
performance/high-functionality systems even for applications such as realtime control, which
could not previously be handled by microcontrollers because of their high-speed processing
requirements.
This LSI is equipped with a media access controller (MAC) conforming to the IEEE802.3u
standard, and an Ethernet controller that includes a media independent interface (MII) standard
unit, enabling 10/100 Mbps LAN connection. Supporting functions necessary for system
configuration are also provided, including cache memory, RAM, timers, a serial communication
interface with FIFO (SCIF), host interface (HFI), interrupt controller (INTC), and I/O ports.
The external memory access support function of this LSI enables direct connection to various
types of memory, such as standard memory, SDRAM, and PCMCIA. This greatly reduces system
cost.
Rev. 6.00 Jun. 12, 2007 Page 1 of 610
REJ09B0131-0600