SH7618 Datasheet, PDF (77/646 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7618 Series

Section 2 CPU
Instruction
Operation
Code
Execution
Cycles
BRAF Rm
Delayed branch,
Rm + PC → PC
0000mmmm00100011 2
BSR label
Delayed branch, PC → PR, 1011dddddddddddd 2
disp × 2 + PC → PC
BSRF Rm
Delayed branch, PC → PR, 0000mmmm00000011 2
Rm + PC → PC
JMP @Rm
Delayed branch, Rm → PC 0100mmmm00101011 2
JSR @Rm
Delayed branch, PC → PR, 0100mmmm00001011 2
Rm → PC
RTS
Delayed branch, PR → PC 0000000000001011 2
Note: * One cycle when the branch is not executed.
T Bit
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• System Control Instructions
Instruction
CLRT
CLRMAC
LDC Rm,SR
LDC Rm,GBR
LDC Rm,VBR
LDC.L @Rm+,SR
LDC.L @Rm+,GBR
LDC.L @Rm+,VBR
LDS Rm,MACH
LDS Rm,MACL
LDS Rm,PR
LDS.L @Rm+,MACH
LDS.L @Rm+,MACL
LDS.L @Rm+,PR
Operation
Code
0→T
0000000000001000
0 → MACH, MACL
0000000000101000
Rm → SR
0100mmmm00001110
Rm → GBR
0100mmmm00011110
Rm → VBR
0100mmmm00101110
(Rm) → SR, Rm + 4 → Rm 0100mmmm00000111
(Rm) → GBR, Rm + 4 →
Rm
0100mmmm00010111
(Rm) → VBR, Rm + 4 →
Rm
0100mmmm00100111
Rm → MACH
0100mmmm00001010
Rm → MACL
0100mmmm00011010
Rm → PR
0100mmmm00101010
(Rm) → MACH, Rm + 4 → 0100mmmm00000110
Rm
(Rm) → MACL, Rm + 4 → 0100mmmm00010110
Rm
(Rm) → PR, Rm + 4 → Rm 0100mmmm00100110
Execution
Cycles
1
1
6
4
4
8
4
4
1
1
1
1
1
1
T Bit
0
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LSB
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LSB
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Rev. 6.00 Jun. 12, 2007 Page 45 of 610
REJ09B0131-0600