SH7618 Datasheet, PDF (29/646 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7618 Series

Tables
Section 1 Overview
Table 1.1 Pin Functions ............................................................................................................ 8
Table 1.2 Pin Features ............................................................................................................ 13
Section 2 CPU
Table 2.1 Initial Values of Registers....................................................................................... 23
Table 2.2 Word Data Sign Extension...................................................................................... 25
Table 2.3 Delayed Branch Instructions................................................................................... 26
Table 2.4 T Bit ........................................................................................................................ 26
Table 2.5 Access to Immediate Data ...................................................................................... 27
Table 2.6 Access to Absolute Address.................................................................................... 27
Table 2.7 Access with Displacement ...................................................................................... 28
Table 2.8 Addressing Modes and Effective Addresses........................................................... 28
Table 2.9 Instruction Formats ................................................................................................. 32
Table 2.10 Instruction Types .................................................................................................... 35
Section 3 Cache
Table 3.1 LRU and Way to be Replaced ................................................................................ 50
Table 3.2 Correspondence between Divided Areas and Cache............................................... 51
Section 5 Exception Handling
Table 5.1 Types of Exceptions and Priority............................................................................ 65
Table 5.2 Timing for Exception Detection and Start of Exception Handling ......................... 66
Table 5.3 Vector Numbers and Vector Table Address Offsets............................................... 67
Table 5.4 Calculating Exception Handling Vector Table Addresses ...................................... 68
Table 5.5 Reset Status............................................................................................................. 69
Table 5.6 Bus Cycles and Address Errors............................................................................... 71
Table 5.7 Interrupt Sources..................................................................................................... 72
Table 5.8 Interrupt Priority ..................................................................................................... 73
Table 5.9 Types of Exceptions Triggered by Instructions ...................................................... 74
Table 5.10 Delay Slot Instructions, Interrupt Disabled Instructions, and Exceptions............... 76
Table 5.11 Stack Status after Exception Handling Ends........................................................... 77
Section 6 Interrupt Controller (INTC)
Table 6.1 Pin Configuration.................................................................................................... 83
Table 6.2 Interrupt Exception Handling Vectors and Priorities.............................................. 98
Table 6.3 Interrupt Response Time....................................................................................... 103
Section 7 Bus State Controller (BSC)
Table 7.1 Pin Configuration.................................................................................................. 108
Rev. 6.00 Jun. 12, 2007 Page xxix of xxxii