SH7618 Datasheet, PDF (353/646 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7618 Series

13.5 Usage Notes
Section 13 Compare Match Timer (CMT)
13.5.1 Conflict between Write and Compare-Match Processes of CMCNT
When the compare match signal is generated in the T2 cycle while writing to CMCNT, clearing
CMCNT has priority over writing to it. In this case, CMCNT is not written to. Figure 13.5 shows
the timing to clear the CMCNT counter.
Peripheral operating
clock (Pφ)
CMCSR write cycle
T1
T2
Address
CMCNT
Internal write
Counter clear
CMCNT
N
H'0000
Figure 13.5 Conflict between Write and Compare-Match Processes of CMCNT
Rev. 6.00 Jun. 12, 2007 Page 321 of 610
REJ09B0131-0600