SH7618 Datasheet, PDF (91/646 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7618 Series

Section 3 Cache
used to invalidate a specific entry in the cache. When the U bit of the entry that has had a hit is 1 at
this time, writing back should be performed. However, when 0 is written to the V bit, 0 must also
be written to the U bit of that entry.
3.4.2 Data Array
The data array is allocated to H'F1000000 to H'F1FFFFFF. To access a data array, the 32-bit
address field (for read/write accesses) and 32-bit data field (for write accesses) must be specified.
The address field specifies information for selecting the entry to be accessed; the data field
specifies the longword data to be written to the data array.
In the address field, specify the entry address for selecting the entry, L for indicating the longword
position within the (16-byte) line, W for selecting the way, and H'F1 for indicating data array
access. As for L, 00 indicates longword 0, 01 indicates longword 1, 10 indicates longword 2,
and 11 indicates longword 3. As for W, 00 indicates way 0, 01 indicates way 1, 10 indicates
way 2, and 11 indicates way 3.
Since access size of the data array is fixed at longword, bits 1 and 0 of the address field should be
set to 00.
Figure 3.4 shows the address and data formats.
The following two operations on the data array are available. The information in the address array
is not affected by these operations.
Data-Array Read: Read the data specified by L of the address field, from the entry that
corresponds to the entry address and the way that is specified by the address field.
Data-Array Write: Write the longword data specified by the data field, to the position specified
by L of the address field, in the entry that corresponds to the entry address and the way specified
by the address field.
Rev. 6.00 Jun. 12, 2007 Page 59 of 610
REJ09B0131-0600