SH7618 Datasheet, PDF (41/646 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7618 Series

Section 1 Overview
Classifi-
cation Abbr.
I/O Pin Name Description
System
control
RES
Input Power-On
Reset
This LSI enters the reset state when this signal goes low.
Interrupt NMI
Input Non-Maskable Non-maskable interrupt request signal. When this pin is not
Interrupt
in use, this signal must be fixed high.
IRQ7 to
IRQ0
Input
Interrupt
Maskable interrupt request pins.
Request 7 to 0 _{Level-input or edge-input detection can be selected. When}
the edge-input detection is selected, the rising or falling edge
can also be selected.
Address A25 to A0 Output Address Bus Outputs addresses.
bus
Data bus D15 to D0 Input/ Data Bus
output
16-bit bidirectional bus
Bus
control
CS0, CS3, Output Chip Select 0, Chip select signals for external memory and devices.
CS4, CS5B,
3, 4, 5B, 6B
CS6B
RD
Output Read
Indicates that data is read from an external device.
RD/WR
BS
Output Read/Write
Output Bus Cycle
Start
Read/write signal
Indicates start of a bus cycle.
WE1
WE0
Output Upper Side
Write
Output Lower Side
Write
Indicates that bits 15 to 8 of data of external memory or
devices are written to.
Indicates that bits 7 to 0 of data of external memory or
devices are written to.
WAIT
Input Wait
Input pin used to insert wait cycles when accessing the
external space
RAS
Output RAS
Connects to the RAS pin of SDRAM.
CAS
Output CAS
Connects to the CAS pin of SDRAM.
CKE
Output Clock Enable Connects to the CKE pin of SDRAM.
DQMLU
Output Upper Side
Select
Selects bits 15 to 8 of SDRAM data bus.
DQMLL
CE1A
Output Lower Side
Select
Selects bits 7 to 0 of SDRAM data bus.
Output PCMCIA Card Chip enable for PCMCIA allocated to area 5
Select Lower
Side
Rev. 6.00 Jun. 12, 2007 Page 9 of 610
REJ09B0131-0600