SH7618 Datasheet, PDF (347/646 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7618 Series

Section 13 Compare Match Timer (CMT)
Section 13 Compare Match Timer (CMT)
This LSI has an on-chip compare match timer (CMT) consisting of a 2-channel 16-bit timer. The
CMT has a16-bit counter, and can generate interrupts at set intervals.
13.1 Features
CMT has the following features.
• Selection of four counter input clocks
Any of four internal clocks (Pφ/8, Pφ/32, Pφ/128, and Pφ/512) can be selected independently
for each channel.
• Interrupt request on compare match
• When not in use, CMT can be stopped by halting its clock supply to reduce power
consumption.
Figure 13.1 shows a block diagram of CMT.
CMI0
Pφ/32
Pφ/512
Pφ/8
Pφ/128
Control circuit
Clock selection
CMI1
Pφ/32
Pφ/512
Pφ/8
Pφ/128
Control circuit
Clock selection
Channel 0
Module bus
[Legend]
CMSTR:
CMCSR:
CMCOR:
CMCNT:
CMI:
CMT
Compare match timer start register
Compare match timer control/status register
Compare match timer constant register
Compare match counter
Compare match interrupt
Channel 1
Bus
interface
Internal bus
Figure 13.1 Block Diagram of Compare Match Timer
TIMCMT3A_000020030900
Rev. 6.00 Jun. 12, 2007 Page 315 of 610
REJ09B0131-0600