SH7618 Datasheet, PDF (536/646 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7618 Series

Section 19 User Debugging Interface (H-UDI)
19.4 Operation
19.4.1 TAP Controller
Figure 19.2 shows the internal states of the TAP controller. State transitions basically conform to
the JTAG standard.
1 Test-logic-reset
0
1
0 Run-test/idle
1
Select-DR-scan
0
1
Capture-DR
0
Shift-DR 0
1
1
Exit1-DR
0
Pause-DR 0
1
0
Exit2-DR
1
Update-DR
1
0
1
Select-IR-scan
0
1
Capture-IR
0
Shift-IR
0
1
1
Exit1-IR
0
Pause-IR 0
1
0
Exit2-IR
1
Update-IR
1
0
Figure 19.2 TAP Controller State Transitions
Note:
The transition condition is the TMS value at the rising edge of the TCK signal. The TDI
value is sampled at the rising edge of the TCK signal and is shifted at the falling edge of
the TCK signal. For details on change timing of the TDO value, see section 19.4.3, TDO
Output Timing. The TDO pin is high impedance, except in the shift-DR and shift-IR
states. A transition to the Test-Logic-Reset state is made asynchronously with TCK by
driving the TRST signal 0.
Rev. 6.00 Jun. 12, 2007 Page 504 of 610
REJ09B0131-0600