SH7618 Datasheet, PDF (81/646 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7618 Series

Section 3 Cache
Section 3 Cache
3.1 Features
• Capacity: 4 kbytes (SH7618), 16 kbytes (SH7618A)
• Structure: Instructions/data unified, 4-way set associative
• Line size: 16 bytes
• Number of entries: 64 entries/way (SH7618), 256 entries/way (SH7618A)
• Write method: Write-back/write-through is selectable
• Replacement method: Least-recently-used (LRU) algorithm
3.1.1 Cache Structure
The cache holds both instructions and data and employs a 4-way set associative system. It is
composed of four ways (banks), and each of which is divided into an address section and a data
section. Each of the address and data sections is divided into 64 entries (256 entries for the
SH7618A). The data of an entry is called a line. Each line consists of 16 bytes (4 bytes × 4). The
data capacity per way is 1 kbyte (16 bytes × 64 entries) (4 kbytes (16 bytes × 256 entries) for the
SH7618A), with a total of 4 kbytes (16 kbytes for the SH7618A) in the cache (4 ways).
Figure 3.1 shows the cache structure.
Address array (ways 0 to 3)
Data array (ways 0 to 3)
LRU
Entry 0 _{V U Tag address}
0 _{LW0 LW1 LW2 LW3}
0
Entry 1
1
1
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Entry 63
(Entry 255)*
24 (1 + 1 + 22) bits
Note: * For the SH7618A.
63
(255)*
128 (32 × 4) bits
LW0 to LW3: Longword data 0 to 3
Figure 3.1 Cache Structure
63
(255)*
6 bits
CACH000C_000020030900
Rev. 6.00 Jun. 12, 2007 Page 49 of 610
REJ09B0131-0600