SH7618 Datasheet, PDF (319/646 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7618 Series

Section 12 Ethernet Controller Direct Memory Access Controller (E-DMAC)
(2) Receive Descriptor
Figure 12.3 shows the relationship between a receive descriptor and the receive buffer. In frame
reception, the E-DMAC performs data rewriting up to a receive buffer 16-byte boundary,
regardless of the receive frame length. Finally, the actual receive frame length is reported in the
lower 16 bits of RD1 in the descriptor. Data transfer to the receive buffer is performed
automatically by the E-DMAC to give a one frame/one buffer or one frame/multi-buffer
configuration according to the size of one received frame.
Receive descriptor
31 30 29 28 27 26
0
R RR RR
RD0 ^{A D F F F}
C LP PE
RFS26 to RFS0
TE1 0
RBL
15
0
RD1
31
16
RDL
31
0
RD2
RBA
Padding (4 bytes)
Receive buffer
Valid receive data
Figure 12.3 Relationship between Receive Descriptor and Receive Buffer
Rev. 6.00 Jun. 12, 2007 Page 287 of 610
REJ09B0131-0600