SH7618 Datasheet, PDF (432/646 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7618 Series

Section 15 Host Interface (HIF)
Bit
7
6
5
4 to 2
1
0
Bit Name
—
—
MD1
—
EDN
BO
Initial
Value
0
1
0/1
All 0
0
0
R/W Description
R
Reserved
This bit is always read as 0. The write value should
always be 0.
R
Reserved
This bit is always read as 1. The write value should
always be 1.
R
HIF Mode 1
Indicates whether this LSI was started up in HIF boot
mode or non-HIF boot mode. This bit stores the value
of the HIFMD pin sampled at a power-on reset
0: Started up in non-HIF boot mode (booted from the
memory connected to area 0)
1: Started up in HIF boot mode (booted from HIFRAM)
R
Reserved
These bits are always read as 0. The write value
should always be 0.
R/W Endian for HIFRAM Access
Specifies the byte order when HIFRAM is accessed by
the on-chip CPU.
0: Big endian (MSB first)
1: Little endian (LSB first)
R/W Byte Order for Access of All HIF Registers Including
HIFDATA
Specifies the byte order when an external device
accesses all HIF registers including HIFDATA.
0: Big endian (MSB first)
1: Little endian (LSB first)
Rev. 6.00 Jun. 12, 2007 Page 400 of 610
REJ09B0131-0600