SH7618 Datasheet, PDF (143/646 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7618 Series

Section 7 Bus State Controller (BSC)
Physical Address
Area
Memory to be Connected
Capacity
H'10000000 to H'13FFFFFF Area 4 Normal memory
64 Mbytes
Byte-selection SRAM
H'14000000 to H'15FFFFFF Area 5A Reserved area*
32 Mbytes
H'16000000 to H'17FFFFFF Area 5B Normal memory
32 Mbytes
Byte-selection SRAM
H'18000000 to H'19FFFFFF Area 6A Reserved area*
32 Mbytes
H'1A000000 to H'1BFFFFFF Area 6B Normal memory
32 Mbytes
Byte-selection SRAM
H'1C000000 to H'1FFFFFFF Area 7 Reserved area*
64 Mbytes
Note: * Do not access the reserved area. If the reserved area is accessed, the correct operation
cannot be guaranteed.
Table 7.3 Address Map 2 (CMNCR.MAP = 1)
Physical Address
Area
Memory to be Connected
Capacity
H'00000000 to H'03FFFFFF
H'04000000 to H'07FFFFFF
H'08000000 to H'0BFFFFFF
Area 0
Area 1
Area 2
Normal memory
Reserved area*¹
Reserved area*¹
64 Mbytes
64 Mbytes
64 Mbytes
H'0C000000 to H'0FFFFFFF Area 3 Normal memory
64 Mbytes
Byte-selection SRAM
SDRAM
H'10000000 to H'13FFFFFF Area 4 Normal memory
64 Mbytes
Byte-selection SRAM
H'14000000 to H'17FFFFFF Area 5*² Normal memory
64 Mbytes
Byte-selection SRAM
H'18000000 to H'1BFFFFFF
Area 6*²
PCMCIA
Normal memory
64 Mbytes
Byte-selection SRAM
H'1C000000 to H'1FFFFFFF Area 7
PCMCIA
Reserved area*¹
64 Mbytes
Notes: 1. Do not access the reserved area. If the reserved area is accessed, the correct operation
cannot be guaranteed.
2. For area 5, CS5BBCR and CS5BWCR are enabled.
For area 6, CS6BBCR and CS6BWCR are enabled.
Rev. 6.00 Jun. 12, 2007 Page 111 of 610
REJ09B0131-0600