SH7618 Datasheet, PDF (386/646 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7618 Series

Section 14 Serial Communication Interface with FIFO (SCIF)
Initial
Bit
Bit Name value R/W Description
7
RTRG1
0
R/W Receive FIFO Data Trigger
6
RTRG0
0
R/W Set the specified receive trigger number. The receive
data full (RDF) flag in the serial status register (SCFSR)
is set when the number of receive data stored in the
receive FIFO register (SCFRDR) exceeds the specified
trigger number shown below.
• Asynchronous mode
00: 1
01: 4
10: 8
11: 14
• Synchronous mode
00: 1
01: 2
10: 8
11: 14
5
TTRG1
0
R/W Transmit FIFO Data Trigger 1 and 0
4
TTRG0
0
R/W Set the specified transmit trigger number. The transmit
FIFO data register empty (TDFE) flag in the serial
status register (SCFSR) is set when the number of
transmit data in the transmit FIFO data register
(SCFTDR) becomes less than the specified trigger
number shown below.
00: 8 (8)*
01: 4 (12)*
10: 2 (14)*
11: 0 (16)*
Note: * Values in parentheses mean the number of
remaining bytes in SCFTDR when the TDFE
flag is set to 1.
Rev. 6.00 Jun. 12, 2007 Page 354 of 610
REJ09B0131-0600