SH7618 Datasheet, PDF (15/646 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7618 Series

11.4.1 Transmission......................................................................................................... 247
11.4.2 Reception .............................................................................................................. 249
11.4.3 MII Frame Timing ................................................................................................ 250
11.4.4 Accessing MII Registers ....................................................................................... 252
11.4.5 Magic Packet Detection ........................................................................................ 255
11.4.6 Operation by IPG Setting...................................................................................... 256
11.4.7 Flow Control......................................................................................................... 256
11.5 Connection to PHY-LSI..................................................................................................... 257
11.6 Usage Notes ....................................................................................................................... 258
Section 12 Ethernet Controller Direct Memory Access Controller
(E-DMAC) .......................................................................................259
12.1 Features.............................................................................................................................. 259
12.2 Register Descriptions ......................................................................................................... 260
12.2.1 E-DMAC Mode Register (EDMR) ....................................................................... 261
12.2.2 E-DMAC Transmit Request Register (EDTRR)................................................... 262
12.2.3 E-DMAC Receive Request Register (EDRRR) .................................................... 263
12.2.4 Transmit Descriptor List Address Register (TDLAR).......................................... 264
12.2.5 Receive Descriptor List Address Register (RDLAR) ........................................... 264
12.2.6 EtherC/E-DMAC Status Register (EESR) ............................................................ 265
12.2.7 EtherC/E-DMAC Status Interrupt Permission Register (EESIPR) ....................... 270
12.2.8 Transmit/Receive Status Copy Enable Register (TRSCER)................................. 273
12.2.9 Receive Missed-Frame Counter Register (RMFCR) ............................................ 275
12.2.10 Transmit FIFO Threshold Register (TFTR).......................................................... 275
12.2.11 FIFO Depth Register (FDR) ................................................................................. 277
12.2.12 Receiving method Control Register (RMCR)....................................................... 278
12.2.13 E-DMAC Operation Control Register (EDOCR) ................................................. 279
12.2.14 Receiving-Buffer Write Address Register (RBWAR) .......................................... 280
12.2.15 Receiving-Descriptor Fetch Address Register (RDFAR) ..................................... 280
12.2.16 Transmission-Buffer Read Address Register (TBRAR)....................................... 280
12.2.17 Transmission-Descriptor Fetch Address Register (TDFAR) ................................ 281
12.2.18 Flow Control FIFO Threshold Register (FCFTR) ................................................ 281
12.2.19 Transmit Interrupt Register (TRIMD) .................................................................. 282
12.3 Operation ........................................................................................................................... 283
12.3.1 Descriptor List and Data Buffers .......................................................................... 283
12.3.2 Transmission......................................................................................................... 291
12.3.3 Reception .............................................................................................................. 293
12.3.4 Multi-Buffer Frame Transmit/Receive Processing ............................................... 295
12.4 Usage Notes ....................................................................................................................... 297
12.4.1 Usage Notes on SH-Ether EtherC/E-DMAC Status Register (EESR).................. 297
Rev. 6.00 Jun. 12, 2007 Page xv of xxxii