SH7201 Datasheet, PDF (897/1196 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 19 Controller Area Network (RCAN-ET)
19.9.5 Interrupts
As shown in table 19.2, the Mailbox 0 receive interrupt enables the DMAC activation. When an
interrupt is specified as to be activated by the Mailbox 0 receive interrupt and cleared by the
interrupt source at the DMA transfer, up to the message control field 1 (CONTROL1) of Mailbox
0 should be read using the block transfer mode.
Rev. 2.00 Sep. 07, 2007 Page 869 of 1164
REJ09B0321-0200