SH7201 Datasheet, PDF (1185/1196 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Index
Numerics
16-bit counter mode................................ 614
16-bit/32-bit displacement ........................ 29
8-bit timers (TMR) ................................. 597
A
A/D conversion time
(multi mode and scan mode)................... 890
A/D conversion time (single mode)........ 889
A/D conversion timing ........................... 889
A/D converter (ADC) ............................. 871
A/D converter activation......................... 535
A/D converter characteristics................ 1142
A/D converter start request
delaying function .................................... 525
A/D trigger input timing ....................... 1137
Absolute address....................................... 29
Absolute address accessing....................... 29
Absolute maximum ratings................... 1101
AC characteristics................................. 1110
AC characteristics measurement
conditions ............................................. 1141
Address array.................................. 184, 196
Address array read .................................. 196
Address errors......................................... 101
Address map ........................................... 205
Address map for each mailbox ............... 811
Address-array write
(associative operation) ............................ 197
Address-array write
(non-associative operation)..................... 197
Addressing modes..................................... 30
Advanced User Debugger II
(AUD-II)............................................... 1021
Analog input pin ratings ......................... 895
Arithmetic operation instructions ............. 48
B
Bit manipulation instructions .................... 59
Bit synchronous circuit ........................... 763
Block diagram............................................. 9
Branch instructions ................................... 53
Break detection and processing............... 723
Break on data access cycle...................... 175
Break on instruction fetch cycle.............. 174
Bus state controller (BSC) ...................... 201
Bus timing............................................. 1116
C
Cache ...................................................... 183
Calculating exception handling
vector table addresses ............................... 96
CAN interface ......................................... 809
CAN sleep mode ..................................... 855
Canceling software standby mode .......... 629
Cascaded connection............................... 614
Changing the division ratio ....................... 88
Changing the frequency .................... 87, 629
Changing the multiplication rate............... 87
Clock frequency control circuit................. 75
Clock operating modes ............................. 77
Clock pulse generator (CPG) .................... 73
Clock timing ......................................... 1110
Clocked synchronous serial format......... 753
Coherency of cache and
external memory ..................................... 196
Compare match count mode ................... 615
Compare match signal............................. 612
Complementary PWM mode .................. 489
Control signal timing ............................ 1114
Controller area network (RCAN-ET)...... 805
CPU........................................................... 19
Rev. 2.00 Sep. 07, 2007 Page 1157 of 1164
REJ09B0321-0200