SH7201 Datasheet, PDF (860/1196 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 19 Controller Area Network (RCAN-ET)
These constraints allow the setting range shown in the table below for TSEG1 and TSEG2 in the
Bit Configuration Register. The number in the table shows possible setting of SJW. "No" shows
that there is no allowed combination of TSEG1 and TSEG2.
Table 19.6 TSG and TSEG Setting
001
010
011
100
101
110
111
TSG2
2
3
4
5
6
7
8
TSEG2
TSG1 TSEG1
0011 4
No
1-3
No
No
No
No
No
0100 5
1-2
1-3
1-4
No
No
No
No
0101 6
1-2
1-3
1-4
1-4
No
No
No
0110 7
1-2
1-3
1-4
1-4
1-4
No
No
0111 8
1-2
1-3
1-4
1-4
1-4
1-4
No
1000 9
1-2
1-3
1-4
1-4
1-4
1-4
1-4
1001 10
1-2
1-3
1-4
1-4
1-4
1-4
1-4
1010 11
1-2
1-3
1-4
1-4
1-4
1-4
1-4
1011 12
1-2
1-3
1-4
1-4
1-4
1-4
1-4
1100 13
1-2
1-3
1-4
1-4
1-4
1-4
1-4
1101 14
1-2
1-3
1-4
1-4
1-4
1-4
1-4
1110 15
1-2
1-3
1-4
1-4
1-4
1-4
1-4
1111 16
1-2
1-3
1-4
1-4
1-4
1-4
1-4
Example 1: To have a Bit rate of 500 Kbps with a frequency of fclk = 40 MHz it is possible to set:
BRP = 3, TSEG1 = 6, TSEG2 = 3.
Then the configuration to write is BCR1 = H'5200 and BCR0 = H'0003.
Example 2: To have a Bit rate of 250 Kbps with a frequency of fclk = 35 MHz it is possible to set:
BRP = 4, TSEG1 = 8, TSEG2 = 5.
Then the configuration to write is BCR1 = H'7400 and BCR0 = H'0004.
Rev. 2.00 Sep. 07, 2007 Page 832 of 1164
REJ09B0321-0200