SH7201 Datasheet, PDF (139/1196 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 5 Exception Handling
5.9 Stack Status after Exception Handling Ends
The status of the stack after exception handling ends is as shown in table 5.12.
Table 5.12 Stack Status After Exception Handling Ends
Exception Type
Address error
Stack Status
SP
Address of instruction
after executed instruction
SR
32 bits
32 bits
Interrupt
SP
Address of instruction
after executed instruction
SR
32 bits
32 bits
Bus error
SP
Address of instruction
after executed instruction
SR
32 bits
32 bits
FPU exception
SP
Address of instruction
after executed instruction
SR
32 bits
32 bits
Register bank error (overflow)
Address of instruction
SP
after executed instruction
SR
32 bits
32 bits
Rev. 2.00 Sep. 07, 2007 Page 111 of 1164
REJ09B0321-0200