SH7201 Datasheet, PDF (156/1196 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 6 Interrupt Controller (INTC)
6.3.9 Bank Number Register (IBNR)
IBNR is a 16-bit register that enables or disables use of register banks and register bank overflow
exception. IBNR also indicates the bank number to which saving is performed next through the
bits BN3 to BN0.
IBNR is initialized to H'0000 by a power-on reset or in deep standby mode.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
BE[1:0] BOVE — — — — — — — — —
BN[3:0]*
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R R R R R R R R R R R R R
Bit
15, 14
Bit Name
BE[1:0]
13
BOVE
12 to 4 
Initial
Value
00
0
All 0
R/W Description
R/W Register Bank Enable
These bits enable or disable use of register banks.
00: Use of register banks is disabled for all interrupts.
The setting of IBCR is ignored.
01: Use of register banks is enabled for all interrupts
except NMI and user break. The setting of IBCR is
ignored.
10: Reserved (setting prohibited)
11: Use of register banks is controlled by the setting of
IBCR.
R/W Register Bank Overflow Enable
Enables of disables register bank overflow exception.
0: Generation of register bank overflow exception is
disabled
1: Generation of register bank overflow exception is
enabled
R Reserved
These bits are always read as 0. The write value should
always be 0.
Rev. 2.00 Sep. 07, 2007 Page 128 of 1164
REJ09B0321-0200