SH7201 Datasheet, PDF (299/1196 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 9 Bus State Controller (BSC)
Multiple write
CKIO
SDRAM command
ACT DSL WR WR WR WR PRA DSL
Data bus
d0
d1
d2
d3
DRCD
(ACR-WR)
DWR
DPCG
(WR-PRA) (PRA-next)
DRAS
(ACT-PRA)
ACT: Row and bank activation command
WR: Write command
PRA: Precharge-all command
Figure 9.34 Multiple Write Timing Example 2
Multiple write
CKIO
SDRAM command
ACT DSL WR WR WR WR DSL PRA DSL
Data bus
d0
d1
d2
DRCD
(ACT-WR)
DRAS
(ACT-PRA)
ACT: Row and bank activation command
WR: Write command
PRA: Precharge-all command
d3
DWR
(WR-PRA)
DPCG
(PRA-next)
Figure 9.35 Multiple Write Timing Example 3
• Single Read Timing Setting Examples
Figures 9.36 to 9.38 show the correspondence between the timing of single read operations and
the set values of the SDRAMm timing register (SDmTR). Table 9.14 shows the SDRAMm
timing register (SDmTR) set values for each figure.
Rev. 2.00 Sep. 07, 2007 Page 271 of 1164
REJ09B0321-0200