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SH7201 Datasheet, PDF (1160/1196 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
Section 29 Electrical Characteristics
29.3.9 SCIF Module Timing
Table 29.13 SCIF Module Timing
Conditions: PVCC = VCCR = PLLVCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V,
PVCC − 0.3 V ≤ AVCC ≤ PVCC, AVref = 3.0 V to AVCC,
PVSS = VSSR = PLLVSS = AVSS = 0 V
Item
Symbol Min.
Max.
Unit
Input clock cycle (Clocked synchronous) tScyc
12
(Asynchronous)
4
Input clock rise time
Input clock fall time
Input clock width
Transmit data delay time
(Clocked synchronous)
t
SCKr
t
SCKf
t
SCKW
tTXD
—
—
0.4
—

tpcyc

t
pcyc
1.5
t
pcyc
1.5
t
pcyc
0.6
t
Scyc
3 tpcyc + 15 ns
Receive data setup time
(Clocked synchronous)
tRXS
4 tpcyc + 15 
ns
Receive data hold time
(Clocked synchronous)
tRXH
1 tpcyc + 15 
ns
Note:
t
pcyc
indicates
a
peripheral
clock
(Pφ)
cycle.
Figure
Figure 29.31
Figure 29.32
SCK
tSCKW
tSCKr
tScyc
tSCKf
Figure 29.31 SCK Input Clock Timing
SCK
TxD
(data transmit)
RxD
(data receive)
tScyc
tTXD
tRXS tRXH
Figure 29.32 SCIF Input/Output Timing in Clocked Synchronous Mode
Rev. 2.00 Sep. 07, 2007 Page 1132 of 1164
REJ09B0321-0200