SH7201 Datasheet, PDF (1053/1196 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 27 Advanced User Debugger II (AUD-II)
AUDCK
AUDSYNC
AUDATA[3:0]
0000
1000
A3 to
A0
DIR
Input/output changeover
A31 to
A28
0000
Not Ready
0001
Ready
0001 0001
D3 to
D0
D7 to
D4
Ready Ready
Input
Output
Figure 27.2 Example of Read Operation (Byte Read)
AUDCK
AUDSYNC
AUDATA[3:0]
0000
1110
A3 to
A0
DIR
A31 to D3 to
A28 D0
Input/output changeover
D31 to
D28
0000
Not Ready
0001 0001 0001
Ready Ready Ready
Input
Output
Figure 27.3 Example of Write Operation (Longword Write)
AUDCK
AUDSYNC
AUDATA[3:0]
0000
1010
A3 to
A0
DIR
Input/output changeover
A31 to
A28
0000
0101
Not Ready
Ready
(Bus error)
0101 0101
Ready Ready
(Bus error) (Bus error)
Input
Output
Figure 27.4 Example of Error Occurrence (Longword Read)
Rev. 2.00 Sep. 07, 2007 Page 1025 of 1164
REJ09B0321-0200