SH7201 Datasheet, PDF (1191/1196 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

SCIF module timing ............................. 1132
Searching cache ...................................... 191
Sending a break signal ............................ 723
Serial communication interface
with FIFO (SCIF) ................................... 665
Serial sound interface (SSI) .................... 767
Setting analog input voltage ........... 893, 902
Shift instructions....................................... 52
Sign extension of word data ..................... 26
Single mode ............................................ 880
Slave receive operation........................... 752
Slave transmit operation ......................... 749
Sleep mode ........................................... 1002
Slot illegal instructions ........................... 108
Software standby mode......................... 1003
Stack after interrupt
exception handling.................................. 148
Stack status after exception
handling ends.......................................... 111
Standby control circuit.............................. 75
Status register (SR)................................... 20
System control instructions....................... 54
T
T bit .......................................................... 28
TAP controller ...................................... 1017
Test mode settings .................................. 857
Time quanta is defined............................ 828
Timing to clear an interrupt source ......... 160
Transfer rate............................................ 731
Trap instructions ..................................... 108
Types of exception handling and
priority order ............................................. 91
U
UBC trigger timing ............................... 1128
UDTDO output timing .......................... 1018
Unconditional branch instructions
with no delay slot ...................................... 27
User break controller (UBC)................... 161
User break interrupt ................................ 133
User debugging interface (H-UDI) ....... 1013
Using interval timer mode....................... 631
Using watchdog timer mode ................... 630
V
Vector base register (VBR)....................... 22
W
Watchdog timer (WDT) .......................... 621
Watchdog timer timing ......................... 1131
Write-back buffer
(only for operand cache) ......................... 194
Rev. 2.00 Sep. 07, 2007 Page 1163 of 1164
REJ09B0321-0200