SH7201 Datasheet, PDF (378/1196 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 11 Direct Memory Access Controller (DMAC)
If the DMA byte count reload function enable bit (BRLOD) in the DMA control register A
(DMCNTAn) is set to "1", the DMA current byte count register (DMCBCTn) is reloaded with
the value in the DMA reload byte count register (DMRBCTn).
Note: If reloading is not to be executed, set ECLR = "1" to ensure that the DEN bit is cleared.
11.5.2 DMA Interrupt Requests
The DMAC generates two types of interrupt request signal for the interrupt controller. One
consists of the interrupt request signals for the individual channels (DMINT_N) and the other is
the common interrupt request signal in which the interrupt request signals from all channels are
pooled to produce a common interrupt request signal (DMINTA_N).
Figure 11.4 is a block diagram showing how the per-channel and common interrupt requests are
generated.
When a DMA transfer ends and the DMA interrupt control bit (DINTM) for the corresponding
channel in the DMA interrupt control register (DMICNT) is set to "1", interrupt requests for the
corresponding channel are generated.
Only those channels for which the DMA common interrupt request signal control bit (DINTA) in
the DMA common interrupt control register (DMICNTA) is set to "1" contribute to the output of
common interrupt request.
Once generated, an interrupt request is cleared to "0" by writing a "1" to the corresponding DMA
transfer end condition detection bit (DEDET).
Rev. 2.00 Sep. 07, 2007 Page 350 of 1164
REJ09B0321-0200